1. Field of the Invention
The present invention relates to decoders for decoding multiple instructions in parallel in order to decode multiple macroinstructions and supply multiple micro-operations in parallel.
2. Description of Related Art
Computers process information by executing a sequence of instructions, which may be supplied from a computer program written in a particular format and sequence designed to direct the computer to operate a particular sequence of operations. Most computer programs are written in high level languages such as FORTRAN or "C" which are not directly executable by the computer processor. In order to run these high level programs, the program is compiled by a compiler program that translates the higher level instructions into macroinstructions having a format that can be decoded and executed. The compiled macroinstructions are supplied to a decoder residing within the processor, where each macroinstruction is decoded into one or more micro-operations which are executable by execution units within the microprocessor.
Microinstructions are usually supplied from the decoder one at a time to subsequent processing units. Because a conventional execution unit can execute a maximum of one micro-operation per cycle, a conventional decoder issues a maximum of one micro-operation per cycle. However, recently developed processors include multiple high performance execution units which can consume and execute more than one micro-operation per cycle. These processors include pipelined structures in which multiple instructions are in various stages in the execution unit at any one time and superscalar processors that have two or more independent execution paths. Such processors include out-of-order execution units that have been proposed, for example in "Superscalar Microprocessor Design", by Mike Johnson, Prentice Hall, 1991. At page 19, Johnson discusses in-order issue from a decoder and out-of-order completion.
In order to obtain maximum advantage from parallel execution, the decoder must be able to decode more than one instruction per cycle. Without such a decoder, the usefulness of a high performance execution unit would be drastically reduced.